1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to the testing of integrated circuits.
2. Background of the Invention
As the number of components and the complexity of integrated circuits have increased, the importance of testing these integrated circuits has increased. The importance of testing has become so great that many components in a circuit are now dedicated to the testing (and program debug) involving these circuits. Concurrently, integrated circuits have continually been reduced in size. One of the most important consequences of this size reduction, along with the increased complexity and functionality of the integrated circuit, has been the problem of providing the necessary electrical connections between the integrated circuit and the components not fabricated in the circuit. The testing and program debug associated with the testing of the integrated circuit requires additional terminals. For example, the common Joint Test Action Group (JTAG) boundary scan interface procedure requires up to five terminals to accomplish the specified test procedure.
Referring to FIG. 1A, a system for providing system and test clock signals to a processor core (or any integrated circuit) 101 under test. An oscillator unit 11 supplies a periodic signal to the input terminals of amplifier unit 171 and amplifier unit 172, both of buffer unit 17. The output terminal of amplifier 171 applies a signal to the phase locked loop 102. The signal applied to the phase locked loop 102 results in the phase locked loop providing a system clock (SYSCLK) signal to the integrated circuit 101. The output terminal of amplifier 172 is coupled through element 16 to emulation unit 15. Element 16 is a reverse termination resistor used to compensate for “transmission line” effects. The emulation unit 15 exchanges signals with the interface logic unit 103 (typically called the TAG unit in JTAG literature). One of the signals applied to the interface logic unit from the emulation unit is the TCK (test clock) signal. The interface logic unit 103 exchanges signals with the processor core 101.
Referring to FIG. 1B, a similar block diagram is shown. In this configuration, the system clock is implemented by a crystal oscillator tank circuit 21 including an crystal oscillator 211 external to the integrated circuit 20 and an energy storage element 212 forming part of the integrated circuit 20. The crystal oscillator tank circuit 21 is activated by the oscillator unit 11 and circuit 21 applies system clock signal to the processor core 101. The other interconnections are the same for the two circuits. As will be clear, both FIG. 1A and FIG. 1B include only those components necessary to describe the invention. The configuration is more complicated than is shown in these Figs.
A need has therefore been felt for apparatus and an associated method having the feature of being able to reduce the number of terminals that provide for the interaction of external components with an integrated circuit. It would yet another feature of the apparatus and associated method to reduce the number of terminals providing the timing signals to the integrated circuit. It is yet another feature of the apparatus and associated method to provide system and test signals having the same frequency to an integrated circuit.